Altera expands its Stratix IV GT FPGAs product line by introducing EP4S40G5 and EP4S100G5 high density and system-bandwidth FPGA to meet the demands of bandwidth-heavy applications. These semiconductor devices come with 11.3-Gbps transceivers and 530K logic elements (LEs).
Stratix IV GT FPGAs support hi-tech 40G/100G technologies, including optical transport network (OTN) framers and mappers, 40/100 Gigabit Ethernet (GbE) media access controllers (MACs), and 10G chip-to-chip and chip-to-module bridging applications.
“From a test perspective, building the 100G ecosystem requires reliable functionality from the physical layer upwards. The breadth and depth of 100G applications demands silicon solutions that offer sophisticated and deep functionality, high performance and density,” said Jerry Gentile, senior vice president in JDSU’s communications test and measurement business segment. “Supported by Altera’s Stratix IV GT FPGAs, JDSU test solutions are ready for the comprehensive testing and validation of high-end communication systems with the ability to scale up to the latest communication solutions.”
Stratix IV GT devices meet the emerging IEEE 802.3ba standard for 100G MACs. This is made possible with the incorporated single-chip solution that comes with 11.3-Gbps integrated transceivers to offer direct interface to CFP optical module.
“The increased usage of broadband applications like HDTV and Internet video is placing tremendous strains on older networks that were not designed to manage the amount of traffic these applications generate,” said Luanne Schirrmeister, senior director of component product marketing, Altera Corporation. “This is forcing the telecommunications industry to ramp up their 40G/100G networks as quickly as possible. With Stratix IV GT FPGAs, we deliver a single-chip solution that is specifically optimized to address the high-speed data-rate and bandwidth requirements of this emerging market.”
Stratix IV GT devices come with a low 0.9V core power supply, up to 48 integrated transceivers, on-die and on-packing decoupling, 20.7 Mbits of embedded memory, 1,024 18×18 multipliers, up to 530K Les and up to four hard intellectual property (IP) cores for PCI Express (PCIe) Gen1 and Gen2 (x1, x4 and x8).
They are compatible with a wide range of protocols including GbE, GPON, SFI-5.1, Serial RapidIO, XAUI, CPRI (including 6G CPRI), CEI 6G, and Interlaken.
The Stratix IV GT EP4S40G5 and EP4S100G5 are said to be shipping currently. The availability and pricing details are not yet announced.
