Altera to offer new innovations for 28-nm FPGAs

Altera Logo Altera has unboxed new innovations to be integrated into the upcoming 28-nm FPGAs. The company is all set to improve the density and I/O performance of the latest FPGAs with the embedded 28-Gbps transceivers while the embedded HardCopy Blocks bring in a new method for partial reconfiguration.

The growth of bandwidth-intensive applications like high-definition (HD) video, cloud computing, online data storage and mobile video bring in challenges for infrastructure as well as end-user equipment developers. Altera now resolves these issues with the new innovations which will help increase the bandwidth while maintaining power and cost efficiency.

“Two years ago, Altera introduced the industry’s first 40-nm FPGAs, and continued delivering industry firsts such as embedded 11.3-Gbps transceivers,” said John Daane, president, chairman and CEO of Altera. “As we move to the next process node, these new innovations from Altera will take the industry beyond the benefits of Moore’s Law to solve bandwidth challenges while staying within cost and power requirements.”

Leveraging on Altera’s unique HardCopy ASIC capabilities, the HardCopy Blocks harden standard or logic-intensive functions. While reducing cost and power, they offer faster time to market for their designs. Thus, the company can quickly create various products and also target specific market segments.

On the other hand, partial reconfiguration lets designers reconfigure part of the FPGA while other sections are running. This is useful in systems wherein uptime is critical. Partial reconfiguration lowers power as well as cost. It improves effective logic density and also helps reduce the size of the FPGA enabling multiple applications on a single FPGA.

Altera is said to simplify the partial reconfiguration process with the capability on top of the proven incremental compile design flow in its Quartus II design software. Altera has developed 28-Gbps embedded transceivers which will be integrated with the upcoming 28-nm FPGAs. The high-speed transceivers let users implement next-generation designs like 400G systems on a single chip negating costly external components.